Driving Next-Gen EV Inverters: HV Gate Driver Solutions for 3-Level and GaN Architectures

The race toward higher efficiency, lower EMI, and higher power density is driving major architectural shifts in EV traction inverters, notably the adoption of three-level topologies and wide-bandgap devices such as GaN. This session presents NXP’s perspective on these converging trends and shows how advanced automotive-grade gate drivers enable both 3‑level Si-based and GaN-based inverter platforms.

We will discuss gate driver requirements, safety and protection concepts, and control challenges associated with higher switching speeds and voltages. System-level insights are illustrated through reference designs and results from a joint NXP–ViSiC–AVL collaboration on a 400 V GaN traction inverter, including Si vs. GaN comparisons and PoC learnings.

The session highlights how scalable gate driver solutions can simplify system integration and accelerate the adoption of next-generation inverter architectures.