Why Energy Infrastructure Now Defines the Scalability of AI Data Centers

By, Mudit Srivastava – Data Center Segment Business Program Manager at STMicroelectronics 

At this scale, system performance is no longer limited primarily by compute capability. Instead, power delivery, energy efficiency, and thermal management have become dominant engineering constraints. Supplying electrical energy efficiently and reliably to AI computing elements—while remaining within spatial, thermal, and sustainability limits—has emerged as a first order design challenge for data center architects. Traditional power architectures, optimized for enterprise and cloud workloads of the past, were not designed for these operating conditions. Rising currents, excessive copper usage, increasing conversion losses, and escalating cooling demands now impose fundamental physical and economic limits. Addressing these challenges requires a re architecture of how energy is distributed, converted, and managed within AI data centers. 

AI Rests on Physical Infrastructure: Energy Comes First  

AI is often framed as a software or algorithmic breakthrough, but its scalability ultimately depends on physical infrastructure. Every AI workload consumes energy—whether during large scale model training in hyperscale data centers or real time inference across distributed edge systems. As model complexity increases and deployment expands, cumulative power demand grows rapidly. In both centralized and distributed environments, inefficiencies in power conversion translate directly into heat, cooling overhead, and higher total cost of ownership. 

Beyond computation itself, an AI data center is fundamentally defined by the interaction of three tightly coupled system flows: power flow, thermal flow, and network flow. Power flow concerns how electrical energy is sourced, converted, and delivered to increasingly dense compute elements. Thermal flow governs how the resulting heat is extracted and controlled as rack power levels rise. Network flow enables the massive, low latency data exchange required to interconnect large numbers of processing units into unified AI systems. These flows are interdependent and must evolve coherently as AI infrastructures scale. Energy efficiency therefore becomes inseparable from performance. Losses in power delivery do not simply waste electricity; they limit usable compute density, constrain system scaling, and increase infrastructure cost, while directly influencing thermal behavior and cooling requirements. For this reason, this article places a particular focus on power flow, examining power architectures and power semiconductor technologies as a concrete entry point into the broader engineering challenges of AI data centers—while acknowledging the essential roles of thermal management and high speed connectivity in enabling scalable AI infrastructure, domains in which STMicroelectronics acts as a technology and system level enabler. 

The Limits of Low Voltage Power Distribution

For decades, data centers have relied on low voltage DC distribution, typically based on 48–54 V buses. While effective for traditional server workloads, this approach breaks down as rack power increases substantially. 

Delivering hundreds of kilowatts at low voltage requires extremely high currents, leading to several compounding challenges: Large copper busbars and cabling volumes, High resistive losses and reduced efficiency, Severe thermal stress and cooling complexity, Practical limits on rack scalability. 

These issues are not incremental problems; they represent fundamental physical constraints. Simply increasing conductor size or airflow cannot provide a sustainable path forward for AI scale computing. 

High Voltage DC Architectures Enable AI Scalability

To overcome these limitations, next generation AI data centers are transitioning toward high voltage DC distribution architectures, in which power is delivered to racks at several hundred volts. 

Raising distribution voltage dramatically reduces current for a given power level. An 800 V DC architecture, for example, reduces current by more than an order of magnitude compared with a 54 V system. 

Figure 1 illustrates how this architectural shift yields immediate system level benefits: 

• Lower conduction losses
• Significant reduction in copper usage
• Improved overall energy efficiency
• Greater flexibility for rack level scaling
• Simplified thermal management 

In such architectures, AC to DC conversion is typically centralized upstream, while high voltage DC is distributed directly to the racks. Inside the rack, power is then converted to intermediate and point of load voltages required by processors, accelerators, and memory subsystems. 

Power Semiconductors Enable High Density Conversion  

Achieving efficient, compact conversion at these power levels depends critically on power semiconductor technology. Wide bandgap devices, particularly gallium nitride (GaN), enable higher switching frequencies with lower losses than conventional silicon devices. 

High frequency operation allows smaller magnetic components and higher integration density, both essential for localized conversion. Resonant topologies such as LLC converters are especially attractive due to their soft switching properties and high efficiency. However, operating at high voltage, high frequency, and high power simultaneously introduces challenges in electromagnetic compatibility, thermal management, and magnetic design. 

Figure 3 illustrates a representative high voltage, high frequency DC DC architecture, targeting high density localized 800 V to 50 V DC DC conversion module, highlighting the integration of wide bandgap devices, planar magnetics, and liquid cooling required to reach power densities beyond 2600 W/in³ 

Beyond the initial 800 V to 50 V conversion stage, high voltage DC data center architectures increasingly rely on a portfolio of downstream conversion paths optimized for different server form factors, GPU generations, and thermal envelopes. In response to this diversification, STMicroelectronics has expanded its 800 VDC AI data center power conversion portfolio to include direct 12 V and 6 V architectures, complementing the intermediate 50 V stage and allowing power delivery to move closer to advanced processors. These additional voltage domains reduce the number of conversion stages, limit copper usage, and improve electrical and thermal efficiency at both rack and server levels. 

This portfolio approach has been developed in collaboration with Nvidia, aligned with emerging 800 VDC reference architectures for next generation AI infrastructure. 

These solutions establish a coherent end to end power delivery portfolio spanning multiple voltage domains required in gigawatt scale compute environments, leveraging ST’s power, analog, and mixed signal technologies with custom optimization at both chip and package levels. 

System Level Optimization Beyond Individual Devices  

At megawatt scale rack power, optimization cannot be performed at the component level alone. Power devices, drivers, controllers, magnetics, cooling systems, and mechanical integration are tightly coupled. Improvements in one area affect losses, temperatures, and reliability in others. 

Moreover, practical considerations such as manufacturability, serviceability, sustainability, and recyclability increasingly shape architecture decisions. AI data center power systems must scale reliably over long operational lifetimes while aligning with environmental and regulatory requirements. 

This reality necessitates a system level approach to power electronics, in which semiconductor technologies are designed and deployed with full awareness of their role in the complete energy chain.